I want to make the vivado project, use github, analogdevicesinc/hdl. I have the vivado-2019.1. i don't know which commit I should pull from analogdevicesinc/hdl. can I find the requid version info from the git commit ..read more

Hi , Here we are implementing the same design with Multiple AD9361 on our board, which is not a ZCU102. We are having a user clock with a frequency of 40 MHz which is a single-ended clock. Could you please confirm if this clock frequency can be used as the ref_clk ..read more

M=4, L=8 is the “standard” devicetree for ZCU102+AD9081. Full source here https://github.com/analogdevicesinc/linux/blob/main/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9081.dts You can see the configuration of the data paths in the trx0_ad9081 node. Basically each ADCs and DAC gets 1 CDDC/CDUC and FDDC/FDUC. So 2x ADC and 2x DACs enabled. Syntax is here: https://wiki.analog.com/resources/tools-software/linux-drivers/iio-mxfe/ad9081#device_tree_customization -Travis ..read more

Hi, Just following up on this. Thank you ..read more

Hi, 1. comparing the system_constr.xdc with the eval board schematic, mcs_sync outputs to FMC_HPC0_LA18_CC_P, which routes to SYNC_IN. Looking at the AD9361 datasheet, SYNC_IN is: "Input to Synchronize Digital Clocks Between Multiple AD9361 Devices. If this pin is unused, tied it to ground" (notice that the eval board has a passive pull-down (R111) in this pin). 2. I don't think that would work. In general we use a dedicated clock source, either external or embedded to the evaluation board (e.g. hmc7044 ..read more

Hi, I am currently working on the fmcomms5--->zcu102 project (with 2 AD9361 core) and I have a couple of questions regarding the "system_top" code. Firstly, could you please explain the significance and functionality of the synchronisation code present in the "system_top" module? I would like to understand its role and how it contributes to the overall functionality of our project. Secondly, I am curious about the possibility of using the PL clock (100MHz) instead of the ref_clk. What would be the implications of this change? Would it affect the synchronization or any other aspects of our d ..read more

Hi lcy0110 , JMarques created a fix for this issue, there you can find his explanation as well: https://github.com/analogdevicesinc/testbenches/pull/98 . I tried this on Windows and Linux, both work, no problem. Rebase the util_pack branch onto this one, and you should be able to run it with the ignore version check enabled. Regards, -Istvan ..read more

Hi Jagadheesh , The build guide is available here: https://wiki.analog.com/resources/no-os/build?rev=1709027384 For building a no-OS project you have to follow the steps there (pay attention to Build Prerequisites). There is no problem in using a Vitis version that is a bit older than the one of Vivado. Regards, George ..read more

JMarques iulia Please help me in solving this first. Then I'll look in to working with used defined block ..read more

Hello, I have the AD4698 in QuadSDO mode. After configuration as per the data sheet, when I give the conv pulse and put CS to low, the SDO lines stay high indicating ADC oft busy. This state remains and sometimes switches between SDO to GP1, 2, GP3 lines. I read back successfully all the registered I configured. I have tried almost everything and it just won't get out of busy and eyeb i force sck I get no samples. Please help. Giri ..read more